Semiconductor memory circuits require a regulated voltage, typically supplied by a voltage regulator, which regulates a voltage input from a charge pump. Various types of voltage regulators, including those utilizing capacitor dividers, are well known in the art. FIG. 1 shows a capacitor divider in a conventional voltage regulator. Regulator 100 includes a capacitor divider 110 including high and low capacitors 120 and 130 coupled in series between two voltage sources V.sub.pp and V.sub.ss. The common electrical node between high and low capacitors 120 and 130 is a divider output line 140 which is an input line to comparator 160 and carries a varying voltage of V.sub.div. A reference line 150 having a reference voltage V.sub.ref asserted thereon is the second input line to comparator 160. Comparator 160 asserts a signal onto comparator output line 170 which is coupled to a control gate of transistor 180 which has a source coupled to V.sub.ss and a drain coupled to V.sub.pp.
Maintaining a constant capacitive ratio (k) of the capacitor divider 110 as defined by equation 1 improves the performance of capacitor divider 110 and regulator 100. EQU K=C1/(C1+C2) (1)
Where:
C1=Capacitance of high capacitor 120, and PA1 C2=Capacitance of low capacitor 130.
Capacitors 120, 130 are typically conventional N-well or P-well MOS structures, whose capacitance depends on the state at the semiconductor surface, i.e., whether the MOS capacitor is in an accumulation, depletion, or inversion state. FIG. 2 shows a typical curve representing the capacitance of an N-well MOS capacitor as a function of the voltage across the capacitor or gate-to-substrate voltage V.sub.gs. As seen from FIG. 2, for positive V.sub.gs, capacitance is essentially voltage-independent when V.sub.gs exceeds a certain positive voltage V.sub.a corresponding to the device being in a strong accumulation state.
Accordingly, because the bias voltage or V.sub.gs for low capacitor 130 is initially zero (since V.sub.div is initially zero volts), low capacitor 130 is not yet in this strong accumulation state (i.e., its well is depleted), and thus capacitance C2 is still voltage dependent. As a result, the accuracy of regulating voltage V.sub.pp decreases. Therefore, it is desirable to have a capacitor structure for use in a voltage regulator that exhibits a constant capacitance even at a zero bias voltage level.
Co-pending applications Ser. No. 09/023,497 (Attorney Docket No. M-5383 US) and Ser. No. 09/047,237 (Attorney Docket No. M-5382 US) provide such a capacitor structure, thereby allowing the voltage regulator circuit to precisely regulate the incoming voltage. By using a P-well floating gate NMOS transistor as the low capacitor 130 in a voltage regulator circuit or other circuit for stabilizing a node, a negative threshold voltage for the capacitor can be obtained by erasing the transistor prior to use, thereby allowing the transistor to turn on even when zero volts is applied to the transistor. As a result, during initial operation of the voltage regulator circuit, the capacitor is already in a state where the capacitance is essentially voltage-independent, corresponding to an inversion state. Thus, by replacing the capacitor connected between ground and one input of the operational amplifier in a conventional voltage regulator circuit with the floating gate capacitor of the co-pending applications, precise voltage regulation is possible even at initialization when the voltage across the capacitor is zero.
The floating gate capacitor according to the co-pending applications, as depicted in FIG. 3, is an NMOS floating gate transistor 30 having N-type drain and source regions 32, 33 formed within a P-well 34. P-well 34 is formed within a deep N-well 35, which in turn is formed within a P-type substrate 36. A polysilicon floating gate 39 overlies a channel region 31 between source and drain regions 32, 33, and a polysilicon control gate 40 overlies floating gate 39, with insulative layer 41 separating control gate 40 from floating gate 39 and insulative layer 42 separating floating gate 39 from channel 31. Source and drain regions 32, 33 are commonly connected to a P+ contact 37 and an N+ contact 38 formed within P-well 34 and N-well 35, respectively.
The floating gate transistor can be erased to obtain the desired negative threshold voltage by applying, for example, zero volts to the control gate 40 of the NMOS transistor and approximately 20 volts to the commonly connected source 32, drain 33, and contact regions 37, 38 to force electrons from the floating gate 39 into the substrate 36. In other words, to carry out the erasing operation, it is necessary to ground the control gate 40 and to simultaneously pass an erase voltage of about 20 volts to the commonly connected source, drain and contact regions for a time sufficient to erase the floating gate 39, and then discharge the erase voltage so the voltage regulator circuit can properly function. However, the generation and supply of this high erase voltage, along with the proper electrical connection of the control gate 40 and commonly connected regions to accomplish the erasing operation requires specialized circuitry, preferably on the same semiconductor substrate as the floating gate transistor and the voltage regulator.
There exists a need for a simple methodology and a device for initial erasure of a floating gate transistor used as a capacitor, to enable implementation of an improved voltage regulator using the floating gate transistor.